Semiconductor manufacturing and packaging have increasingly becoming a challenge for manufacturers of integrated circuits as the dimension of semiconductor devices are shrinking to smaller submicron dimensions. As the peripheral area of a semiconductor die reduces in size, the placement of bonding pads on a semiconductor die possesses a concern that the wires connecting between the bonding pads and the leadframe may be too proximate such that the wires may cross one another and thus cause electrical failures to the semiconductor die.
FIG. 1A shows a conventional packaging technique by packing a semiconductor die on a Lead On Chip (LOC) process. A die 100 is positioned underneath the lead frame 110. A plurality of bonding pads 102 of the die 100 electrically connect to a respective lead 101 of the lead frame 110 through a respective wire 103. Unlike common placement of bonding pads around the periphery of a die, the plurality of bonding pads 102 of the die 100 is a LOC process is placed in the center of the die 100. In FIG. 1B, an adhesive tape 104 is attached in between the die 100 and the leads 101. The leads 101 further connects to the leads 103, which in turn connect to the bonding pads 102 of the die 100.
Referring to FIG. 2A, a die 200 is adhered to the insulating layer 204 by an adhesive tape 205. The bonding pads (not shown) in the die 200 are electrically connected to the leads 201 through wires. In FIG. 2B, the non-circuit-forming face of die 200 is attached to the insulating layer 204 to prevent the short circuit of the die.
A drawback of the conventional approach to adhere an adhesive tape between a lead frame and a semiconductor die is that the placement of bonding pads, either around the periphery, in the center, or at other locations of a semiconductor die may restrict the ability of the adhesive tape to adhere the lead frame and the semiconductor die. An example is the LOC Process which limits the adhesive tape to adhere to bonding pads in the center of a semiconductor die.
Accordingly, it is desirable to have a semiconductor packing technique that provides flexibility as to the placement of bonding pads at a location on a semiconductor die.